The present inventive concept relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having buried wiring by using a selective deposition process.
Semiconductor memory devices can include a cell transistor having stack type word lines. As sizes of semiconductor memory devices are reduced, on-currents of cell transistors can decrease, and physical instability and difficulties in processes may occur due to higher aspect ratios.
A buried word line cell array transistor (BCAT) has a structure wherein a word line is buried in a trench of a semiconductor substrate, and accordingly, the cell area may be decreased. The buried word line may be formed by burying a wiring material in a trench of the semiconductor substrate and etching the wiring material using an etch-back process. When a material having a resistivity of about 100 μΩcm is used for the wiring material, the material may be difficult to be applied to dynamic random access memories (DRAMs) near the 20 nanometer level. In addition, when the wiring material is deposited on the entire surface of the substrate including the trench, a gate insulating layer may be damaged by source gas, and then, a thickness of an effective gate insulating layer, and the leakage current, may increase.